The present invention relates to communication systems, memory systems, and integrated circuit (IC) devices.
Over the last few decades, the use of communication networks has exploded. In the early days of the Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like Facebook processes more than 500 TB of data daily. With such high demands on data and data transfer, existing data communication systems need to be improved to address these needs.
CMOS technology is commonly used to design communication and memory systems. As CMOS technology is scaled down to make circuits and systems run at higher speed and occupy smaller chip (die) area, the operating supply voltage is reduced for lower power. An important factor in device operations is the phase interpolation of clock signals to maintain synchronization of various electronic devices in communication systems. Failure to adjust clock signals without glitches can render systems non-functional. Conventional techniques for updating the phase interpolation of a communications system take too long or are prone to glitching. Limitations such as these provide significant challenges to the continued improvement of communication systems scaling and performance.
Accordingly, improvements to update techniques for phase interpolation in integrated circuit devices are highly desirable.